1. Field of the Invention
The present invention relates in general to electronic memories and in particular, to circuitry and methods for dynamically sensing data in a static random access memory cell.
2. Description of the Related Art
Static random access memory cells (SRAMs) are useful in applications such as cache memory, where speed is a more critical consideration than power consumption and cell size. SRAM memory can be in the form of a discrete device, such as the L2 cache in a processing system, or be embedded within a larger processing device, such as the L1 cache found on-board many microprocessors. Even though speed is the most critical factor, reduced power consumption and noise minimization are always a major concern for the designers of SRAMs and in particular of embedded SRAM design.
One area where power consumption and noise become a particular problem is in the sense amplifier design. Recent trends in embedded high-speed CMOS SRAM memory design have made the traditional analog amplifier sensing schemes less attractive. Among other things, when traditional SRAM amplifiers are outputting data, the DC power consumption rapidly increases. In fact, the sense amplifier power consumption can often represent most of the overall SRAM power consumption. Additionally, traditional SRAM sense amplifiers produce system noise in the form of output switching transients. Not only do these output switching transients create signal transmission problems but, if the outputs of a large number of sense amplifiers are switching, they can also increase power consumption.
Thus, the need has arisen for new SRAM sensing circuitry and methods for constructing low power consumption, low noise SRAMs.